The "mesa" technique is already known in the production of power semiconductor devices having junctions adapted to withstand very high reverse bias. In this technique, a wafer of semiconductor material, usually silicon or germanium in a microcrystalline state, after having been treated with conventional diffusion and photoengraving techniques to form one or more junctions parallel to its faces, is subjected to an etching operation according to a predetermined pattern. The etched areas divide the wafer into a plurality of semiconducting elements or chips which have lateral surfaces intersecting one or more junctions between zones of opposite conductivity types. The slope of the chip flanks is determined during the design of the device in accordance with the principle of minimizing the electrostatic fields which, owing to the difference in polarity and resistivity of the semiconductor layers, are formed on the lateral surface of each semiconducting element. The bevel or inclination of any flank is usually termed positive when, considering two superimposed layers having different resistivity and forming a junction near a face of the mesa, the outer layer of lower resistivity projects beyond the inner layer of higher resistivity, and negative (standard mesa) when the higher-resistivity inner layer projects beyond the outer layer of lower resistivity.
It is known that the electrical properties of the semiconductor devices can be affected by even small amounts of impurities deposited on the surfaces of the semiconductor material when the surfaces remain uncovered during the various operational processing steps, and thus in direct contact with ambient air or other substances. Particularly sensitive to contamination are the zones immediately adjacent to the junctions which, in the case of devices manufactured in accordance with the "mesa" technique, are exposed at the lateral surfaces of each semiconducting element. This problem requires a great deal of care especially when junctions withstanding reverse voltages higher than 1000 volts are to be produced. In that case, it is necessary to provide working conditions characterized by meticulous cleanliness throughout the successive operations following the engraving operation, while taking care that the wafers should be manipulated to the smallest possible extent until they are mounted on their supports and passivated, i.e. completely insulated from the effects of any foreign contaminating agent by being clad in suitable protective materials.
Manufacturing costs for high-reverse-bias devices, already large owing to the specific measures required in handling wafers with unprotected junctions, are further increased by the impossibility of testing the individual semiconducting elements on the still uncut wafer, e.g. by using suitable automatic measuring apparatus, since passivation of the lateral surfaces is a determining factor for the purposes of measuring maximum reverse-bias values to which the junctions may be subjected. Consequently, the overall cost of the finished product is relatively high because elements with pre-existing faults, due to inevitable defects in the crystalline structure of the starting material, or possibly damaged in the various working steps can be rejected only after assembly in the final test.
To avoid the above-described disadvantages, it is necessary to effect passivation immediately after the engraving operation. In this way not only the risk of surface contamination is reduced to a minimum but it is also possible to test the entire wafer, thereby considerably reducing waste of material and labor.
According to a known method of passivating in a single operation all the semiconducting elements in a wafer of semiconductor material, the wafer is fixed at one face thereof to a metallic substrate by means of an electrically conductive adhesive. The wafer is then subdivided into chips without detaching it from the substrate and is thereafter subjected to glass deposition by electrophoresis, whereby the lateral surfaces or flanks of the chips and the parts of the substrate between adjacent chips are covered by a glass layer. This method has some drawbacks which make it difficult to carry it out. In the first place, the adhesive used for fixing the wafer to the substrate can contaminate the chips because it is electrically conductive. In practice, moreover, such adhesives are rarely effective enough to prevent the chips from being prematurely detached during the mechanical cutting of the wafer. Furthermore, the parts of the metallic substrate which remain free after subdivision are covered by a glass layer which is thicker than that covering the lateral parts of the chips, and thus subsequent separation of the chips is rather critical since there is a great risk of cracking, during this operation, the glass covering the junctions, thereby giving access to contaminating agents.